Register Allo ation for Common Subexpressions in DSP Data

Rainer Leupers University of Dortmund Dept. of Computer S ien e 12 D-44221 Dortmund, Germany Rainer.Leupers s.uni-dortmund.de Abstra t| This paper presents a new ode optimization te hnique for DSPs with irregular data path stru tures. We onsider the problem of generating ma hine ode for data ow graphs with ommon subexpressions (CSEs). While in previous work CSEs are supposed to be stri tly stored in memory, the te hnique proposed in this paper also permits the allo ation of spe ial purpose registers for temporarily storing CSEs. As a result, both the ode size and the number of memory a esses are redu ed. The optimization is ontrolled by a simulated annealing algorithm. We demonstrate its e e tiveness for several DSP appli ations and a widespread DSP pro essor. 1 I. Introdu tion More and more embedded systems with DSP fun tionality are based on programmable DSP pro essors. While a pro essor based design style bene ts from high exibility and opportunities for reuse, software development for DSPs still su ers from the fa t, that there is no adequate tool support by C ompilers. Sin e DSPs are tuned for ompute-intensive appli ations, they often show an irregular data path stru ture with di erent fun tional units and spe ial-purpose registers. An example is given in g. 1. The Texas Instruments TMS320C25 is a widespread DSP, whose data path omprises a multiplier, an ALU, three spe ial-purpose registers TR, PR, and ACCU, and a data memory (MEM). Su h domain-spe i ar hite tures pose problems for C ompilers, sin e spe ial onstraints on ode sele tion and register allo ation have to be taken into a ount during ode generation. In ontrast to regular RISC-like data path stru tures, arguments for operations exe uted on fun tional units have to reside in parti ular registers, and extra instru tions may be required for moving values between those registers. In order to illustrate this, onsider the subset of available 'C25 ma hine instru tions in g. 2. Multiplier and ALU results have to be stored in registers PR and ACCU, respe tively, and one multiplier argument has to reside in register TR. Additionally, memory a ess is quite restri ted. For instan e, PR annot be dire tly 1Publi ation: ASP-DAC 2000, Yokohama/Japan, 2000 IEEE TR